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INTEGRATED CIRCUITS
FB2041 7-bit Futurebus+ transceiver
Product specification IC19 Data Handbook 1995 May 25
Philips Semiconductors
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
DESCRIPTION
The FB2041 is a 7-bit bidirectional BTL transceiver and is intended to provide the electrical interface to a high performance wired-OR bus. The FB2041 is an inverting transceiver. The B-port drivers are Low-capacitance open collectors with controlled ramp and are designed to sink 100mA. Precision band gap references on the B-port insure very good noise margins by limiting the switching threshold to a narrow region centered at 1.55V.
* Allows incident wave switching in heavily loaded backplane buses * Reduced BTL voltage swing produces less noise and reduces
power consumption
* Built-in precision band-gap reference provides accurate receiver
thresholds and improved noise immunity
* Compatible with IEEE Futurebus+ or proprietary BTL backplanes * Controlled output ramp and multiple GND pins minimize ground
bounce
FEATURES
* 7-bit BTL transceiver * Separate I/O on TTL A-port * Inverting * Three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit
arrangement
* Drives heavily loaded backplanes with equivalent load
impedances down to 10.
* High drive 100mA BTL open collector drivers on B-port
QUICK REFERENCE DATA
SYMBOL tPLH tPHL tPLH tPHL COB IOL Propagation delay AIn to Bn Propagation delay Bn to AOn Output capacitance (B0 - B6 only) Output current (B0 - B6 only) Standby ICC Supply Current PARAMETER
* Each BTL driver has a dedicated Bus GND for a signal return * Glitch-free power up/power down operation * Low ICC current * Tight output skew * Supports live insertion * Pins for the optional JTAG boundary scan function are provided * High density packaging in plastic Quad Flatpack
TYPICAL 3.7 2.7 3.4 3.2 6 100 19 40 22 19
UNIT ns ns pF mA
AIn to Bn (outputs Low or High) Bn to AOn (outputs Low) Bn to AOn (outputs High)
mA
ORDERING INFORMATION
PACKAGE 52-pin Plastic Quad Flatpack COMMERCIAL RANGE VCC = 5V10%; Tamb = 0 to +70C FB2041BB INDUSTRIAL RANGE VCC = 5V10%; Tamb = -40 to +85C CD3207BB DWG No. SOT379-1
1995 May 25
2
853-1561 15279
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
PIN CONFIGURATION
TCK (option) LOGIC VCC TMS (option) BUS GND BUS VCC
BIAS V
OEA1
OEB0
OEB1
AO1
AO0
52 51 50 49 48 47 46 45 44 43 42 41 40 LOGIC GND AI1 AI2 AO2 LOGIC GND AO3 LOGIC GND AI3 AI4 AO4 LOGIC GND AO5 LOGIC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 LOGIC VCC LOGIC GND LOGIC GND TDO (option) TDI (option) BUS VCC AI5 AO6 AI6 OEA2 OEA3 OEB2 OEB3 39 38 37 36 BUS GND B1 BUS GND B2 BUS GND B3 BUS GND B4 BUS GND B5 BUS GND B6 BUS GND
AI0
7-Bit Transceiver FB2041
B0 35 34 33 32 31 30 29 28 27
52-lead PQFP
The B-port interfaces to "Backplane Transceiver Logic" (See the IEEE 1194.1 BTL standard). BTL features low power consumption by reducing voltage swing (1Vp-p, between 1V and 2V) and reduced capacitive loading by placing an internal series diode on the drivers. BTL also provides incident wave switching, a necessity for high performance backplanes. There are three separate pairs of driver enables in a 1 bit, 3 bit, 3 bit arrangement. The TTL/BTL output drivers for bit 0 are enabled with OEA1/OEB1, output drivers for bits 1-2-3 are enabled with OEA2/OEB2 and output drivers for bits 4-5-6 are enabled with OEA3/OEB3. The A-port operates at TTL levels with separate I/O. The 3-state A-port drivers are enabled when OEAn goes High after an extra 6ns delay which is built in to provide a break-before-make function. When OEAn goes Low, A-port drivers become High impedance without any extra delay. During power on/off cycles, the A-port drivers are held in a High impedance state when VCC is below 2.5V. The B-port has an output enable, OEB0, which affects all seven drivers. When OEB0 is High and OEBn is Low the output driver will be enabled. When OEB0 is Low or if OEBn is High, the B-port drivers will be inactive and at the level of the backplane signal.
To support live insertion, OEB0 is held Low during power on/off cycles to insure glitch free B port drivers. Proper bias for B port drivers during live insertion is provided by the BIAS V pin when at a 5V level while VCC is Low. If live insertion is not a requirement, the BIAS V pin should be tied to a VCC pin. The LOGIC GND and BUS GND pins are isolated in the package to minimize noise coupling between the BTL and TTL sides. These pins should be tied to a common ground external to the package. Each BTL driver has an associated BUS GND pin that acts as a signal return path and these BUS GND pins are internally isolated from each other. In the event of a ground return fault, a "hard" signal failure occurs instead of a pattern dependent error that may be very infrequent and impossible to trouble-shoot. The LOGIC VCC and BUS VCC pins are also isolated internally to minimize noise and may be externally decoupled separately or simply tied together. JTAG boundary scan functionality is provided as an option with signals TMS, TCK, TDI and TDO. When this option is not present, TMS and TCK are no-connects (no bond wires) and TDI and TDO are shorted together internally.
1995 May 25
3
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
PIN DESCRIPTION
SYMBOL AI0 - AI6 AO0 - AO6 B0 - B6 OEB0 OEB1 OEB2 OEB3 OEA1 OEA2 OEA3 BUS GND LOGIC GND BUS VCC LOGIC VCC BIAS V TMS TCK TDI TDO PIN NUMBER 51, 2, 3, 8, 9, 14, 18 50, 52, 4, 6, 10, 12, 16 40, 38, 36, 34, 32, 30, 28 46 45 25 26 47 20 24 41, 39, 37, 35, 33, 31, 29, 27 1, 5, 7, 11, 13, 15, 19 23, 43 17, 49 48 42 44 22 21 TYPE Input Output I/O Input Input Input Input Input Input Input GND GND Power Power Power Input Input Input Output Data inputs (TTL) 3-state outputs (TTL) Data inputs/Open Collector outputs, High current drive (BTL) Enables the Bn outputs when High Enables the B0 output when Low Enables the B1 - B3 outputs when Low Enables the B4 - B6 outputs when Low Enables the A0 outputs when High Enables the A1 - A3 outputs when High Enables the A4 - A6 outputs when High Bus ground (0V) Logic ground (0V) Positive supply voltage Positive supply voltage Positive supply voltage Test Mode Select (no-connect) Test Clock (no-connect) Test Data In (shorted to TDO) Test Data Out (TDI) NAME AND FUNCTION
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the operating free-air temperature range. SYMBOL VCC VIN IIN VOUT IOUT TSTG Supply voltage In ut Input voltage Input current Voltage applied to output in High output state Current applied to output in Low output state Storage temperature AO0 - AO6 B0 - B6 AI0 - AI6, OEB0, OEBn, OEAn B0 - B6 PARAMETER RATING -0.5 to +7.0 -1.2 to +7.0 -1.2 to +5.5 -18 to +5.0 -0.5 to +VCC 48 200 -65 to +150 C mA V mA UNIT V V
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER COMMERCIAL LIMITS VCC = 5V10%; Tamb = 0 to +70C MIN VCC VIH VIL IIK IOH IOL COB Tamb Supply voltage High-level in ut voltage input Low-level in ut voltage input Input clamp current High-level output current Low-level out ut current output Output capacitance on B port Operating free-air temperature range 0 AO0 - AO6 AO0 - AO6 B0 - B6 6 Except B0-B6 B0 - B6 Except B0-B6 B0 - B6 4.5 2.0 1.62 1.55 0.8 1.47 -18 -3 24 100 7 +70 -40 6 TYP 5.0 MAX 5.5 INDUSTRIAL LIMITS VCC = 5V10%; Tamb = -40 to +85C MIN 4.5 2.0 1.62 1.55 0.8 1.47 -18 -3 24 100 7 +85 pF C mA mA mA V TYP 5.0 MAX 5.5 V V UNIT
1995 May 25
4
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
FUNCTION TABLE
MODE AIn L AIn to Bn H L H L AI0 to B0 H L H L AI1 - AI3 to B1 - B3 H L H L AI4 - AI6 to B4 - B6 H L H Disable Bn outputs Disable B0 outputs Disable B1 - B3 outputs Disable B4 - B6 outputs Bn to AOn X X X X X X X X X X B0 to AO0 X X X X B1 - B3 to AO1 - AO3 X X X X B4 - B6 to AO4 - AO6 X X X Disable AOn outputs Disable AO0 outputs Disable AO1 - AO3 outputs Disable AO4 - AO6 outputs NOTES: H= L = X = Z = --= H** = B* = X X X X Bn* -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- X X X X X L H L H L H L H L H L H L H L H X X X X OEB0 H H H H H H H H H H H H H H H H L X H H H L L X X L L X X L L X X L L X X X X X X OEB1 L L L L L L L L X X X X X X X X X H H X X X X H H X X H H X X H H X X H H X X X X Z -- H** B* = = = = INPUTS OEB2 L L L L X X X X L L L L X X X X X H X H X X X H H X X H H X X H H X X H H X X X X OEB3 L L L L X X X X X X X X L L L L X H X X H X X H H X X H H X X H H X X H H X X X X OEA1 L L H H L L H H L L H H L L H H X X X X X H H H H H H H H X X X X X X X X L L X X OEA2 L L H H L L H H L L H H L L H H X X X X X H H H H X X X X H H H H X X X X L X L X OEA3 L L H H L L H H L L H H L L H H X X X X X H H H H X X X X X X X X H H H H L X X L OUTPUTS AOn Z Z L H Z Z L H Z Z L H Z Z L H X X X X X H L H L H L H L H L H L H L H L Z Z Z Z Bn* H** L H** L H** L H** L H** L H** L H** L H** L H** H** H** H** H** Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input X X X X
High voltage level Low voltage level Don't care High-impedance (OFF) state Input not externally driven Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
High-impedance (OFF) state Input not externally driven Goes to level of pull-up voltage Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
1995 May 25
5
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
LOGIC DIAGRAM
OEB0 46
OEB1 OEA1 AI0 AO0
45
47 40 51 50 B0
OEB2
25 20 38 2 52 B1
OEA2 AI1 AO1
36 AI2 AO2 3 4
B2
TTL Levels
AI3 AO3 8 6
34
B3
BTL Levels
OEB3
26 24 32 9 10 B4
OEA3 AI4 AO4
30 AI5 AO5 14 12
B5
28 AI6 AO6 18 16
B6
TMS TCK TDI TDO
42 44 22 21
(Future JTAG Boundary Scan option)
LOGIC VCC LOGIC GND BUS VCC BUS GND BIAS V
= = = = =
17, 49 1, 5, 7, 11, 13, 15, 19 23, 43 27, 29, 31, 33, 35, 37, 39, 41 48
SG00071
1995 May 25
6
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
LIVE INSERTION SPECIFICATIONS
SYMBOL VBIASV IBIASV S VBn ILM IHM IBnPEAK IO OFF OL tGR Bias pin voltage PARAMETER VCC = 0 to 5.25V, Bn = 0 to 2.0V VCC = 0 to 4.75V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V VCC = 4.5 to 5.5V, Bn = 0 to 2.0V, Bias V = 4.5 to 5.5V B0 - B8 = 0V, Bias V = 5.0V B0 - B8 = 2V, Bias V = 4.5 to 5.5V B0 - B8 = 1V, Bias V = 4.5 to 5.5V VCC = 0 to 5.25V, B0 - B8 = 0 to 2.0V, Bias V = 4.5 to 5.5V, OEB0 = 0.8V, tr = 2ns VCC = 0 to 5.25V, OEB0 = 0.8V VCC = 0 to 2.2V, OEB0 = 0 to 5V VCC = 5.0V 1.0 1.35 1.62 1 -1 10 100 100 LIMITS MIN 4.5 TYP MAX 5.5 1 10 2.1 UNIT V mA A V A A mA A ns
Bias pin DC current Bus voltage during prebias Fall current during prebias Rise current during prebias Peak bus current during insertion Power up current Input glitch rejection
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted. SYMBOL IOH IOFF VOH PARAMETER High level output current Power-off output current High-level output voltage Low-level output voltage Input clamp voltage Input current at maximum input voltage g High-level input current OEB0, OEBn, OEAn, AI0 - AI6 OEB0, OEBn, OEAn, AI0 - AI6 B0 - B6 IIL IOZH IOZL IO Low-level input current Off-state output current Off-state output current Output current OEB0, OEBn, OEAn, AI0 - AI6 B0 - B6 AO0 - AO6 AO0 - AO6 AO0 - AO6 only ICCZ (standby) ICC Supply current (total) ICCB, AIn to Bn ICCA, Bn to AOn ICCA, Bn to AOn B0 - B6 B0 - B6 AO0 - AO6 3 AO0 - AO6 VOL VIK II IIH B0 - B6
3
TEST CONDITIONS1 VCC = MAX, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = 0.0V, VIL = MAX, VIH = MIN, VOH = 2.1V VCC = MIN, VIL = MAX, VIH = MIN, IOH = -3mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 24mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 80mA VCC = MIN, VIL = MAX, VIH = MIN, IOL = 100mA VCC = MIN, II = IIK VCC = MAX, VI = GND or 5.5V VCC = MAX, VI = 2.7V VCC = MAX, VI = 2.1V VCC = MAX, VI = 0.5V VCC = MAX, VI = 0.75V VCC = MAX, VO = 2.7V VCC = MAX, VO = 0.5V VCC = MAX VCC = MAX VCC = MAX, outputs Low or High VCC = MAX, outputs Low VCC = MAX, outputs High
LIMITS MIN TYP2 MAX 100 100 2.5 2.85 0.33 .75 1.0 0.5 1.10 1.15 -1.2 50 20 100 -20 -100 50 -50 -30 -55 19 40 22 19 -150 30 60 35 35
UNIT A A V
V V A A
A A A mA
mA
NOTES: 1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type. 2. All typical values are at VCC = 5V, TA = 25C. 3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
1995 May 25
7
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
AC ELECTRICAL CHARACTERISTICS (Commercial)
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ tTLH tTHL tSK(o) Propagation delay, Bn to AOn Output enable time, OEA to AOn Output disable time, OEA to AOn Transition time, AOn Port (10% to 90% or 90% to 10%) Output skew between receivers in same package1 Waveform 1, 2 Waveform 4, 5 Waveform 4, 5 Test Circuit and Waveforms Waveform 3 1.8 1.6 2.2 2.0 1.5 1.8 1.5 1.5 TYP 3.4 3.2 5.0 4.0 3.3 3.0 2.2 2.4 0.4 MAX 5.0 4.9 6.5 6.5 4.8 5.0 3.0 3.0 1.0 B PORT LIMITS SYMBOL PARAMETER Propagation delay, AIn to Bn Enable/disable time, OEB0 to Bn Enable/disable time, OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between drivers in same package1 PARAMETER Propagation delay, AIn to Bn Enable/disable time, OEB0 to Bn Enable/disable time, OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between drivers in same package1 TEST CONDITION Waveform 1, 2 Waveform 2 Waveform 1 Test Circuit and Waveforms Waveform 3 TEST CONDITION Waveform 1, 2 Waveform 2 Waveform 1 Test Circuit and Waveforms Waveform 3 2.5 1.6 2.5 2.0 2.5 2.0 1.0 0.5 Tamb = +25C, VCC = 5V, CD = 30pF, RU = 9 2.4 1.5 2.4 1.9 2.4 1.9 1.0 0.5 3.7 2.7 3.7 3.5 4.0 3.6 1.4 1.1 0.3 RU = 16.5 3.8 2.8 3.8 3.6 4.1 3.7 1.5 1.1 0.3 5.0 4.5 5.0 5.0 5.6 5.6 3.0 3.0 1.0 4.9 4.4 4.9 4.9 5.5 5.5 3.0 3.0 1.0 Tamb = 0 to 70C, VCC = 5V10%, CD = 30pF, RU = 9 1.9 1.5 1.9 1.8 1.9 2.5 1.0 0.5 5.7 5.0 6.4 5.4 5.9 5.9 3.0 3.0 1.0 RU = 16.5 2.0 1.6 2.0 1.9 2.0 2.6 1.0 0.5 5.8 5.1 6.5 5.5 6.0 6.0 3.0 3.0 1.0 UNIT ns ns ns ns ns UNIT ns ns ns ns ns Tamb = 0 to 70C, VCC = 5V10%, CL = 50pF, RL = 500 MIN 1.6 1.6 2.0 1.8 1.2 1.5 1.5 1.5 MAX 5.5 5.0 10.0 8.0 5.0 5.5 3.5 3.5 1.0 ns ns ns ns ns UNIT
tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o) SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o)
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
1995 May 25
8
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
AC ELECTRICAL CHARACTERISTICS (Industrial)
A PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CL = 50pF, RL = 500 MIN tPLH tPHL tPZH tPZL tPHZ tPLZ tTLH tTHL tSK(o) Propagation delay, Bn to AOn Output enable time, OEA to AOn Output disable time, OEA to AOn Transition time, AOn Port (10% to 90% or 90% to 10%) Output skew between receivers in same package1 Waveform 1, 2 Waveform 4, 5 Waveform 4, 5 Test Circuit and Waveforms Waveform 3 1.8 1.6 2.2 2.0 1.5 1.5 1.5 1.5 TYP 3.4 3.2 5.0 4.0 3.3 3.0 2.2 2.4 0.4 MAX 5.0 4.9 6.5 6.5 4.8 5.0 3.0 3.0 1.0 B PORT LIMITS SYMBOL PARAMETER TEST CONDITION Tamb = +25C, VCC = 5V, CD = 30pF, RU = 9 2.4 1.5 2.4 1.9 2.4 1.9 1.0 0.5 3.7 2.7 3.7 3.5 4.0 3.6 1.4 1.1 0.3 RU = 16.5 2.5 1.6 2.5 2.0 2.5 2.0 1.0 0.5 3.8 2.8 3.8 3.6 4.1 3.7 1.5 1.1 0.3 5.0 4.5 5.0 5.0 5.5 5.5 3.0 3.0 1.0 4.9 4.4 4.9 4.9 5.5 5.5 3.0 3.0 1.0 Tamb = -40 to +85C, VCC = 5V10%, CD = 30pF, RU = 9 1.9 1.5 1.9 1.8 1.9 1.5 1.0 0.5 5.9 5.0 6.4 5.9 6.8 6.8 3.0 3.0 1.0 RU = 16.5 2.0 1.6 2.0 1.9 2.0 1.6 1.0 0.5 6.0 5.1 6.5 6.0 6.9 6.9 3.0 3.0 1.0 UNIT Tamb = -40 to +85C, VCC = 5V10%, CL = 50pF, RL = 500 MIN 1.6 1.6 1.5 1.5 0.8 1.2 1.5 1.5 MAX 5.5 5.5 8.0 8.0 6.0 6.0 3.5 3.5 1.0 ns ns ns ns ns UNIT
tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o) SYMBOL tPLH tPHL tPLH tPHL tPLH tPHL tTLH tTHL tSK(o)
Propagation delay, AIn to Bn Enable/disable time, OEB0 to Bn Enable/disable time, OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between drivers in same package1 PARAMETER Propagation delay, AIn to Bn Enable/disable time, OEB0 to Bn Enable/disable time, OEB1 to Bn Transition time, Bn Port (1.3V to 1.8V) Output skew between drivers in same package1
Waveform 1, 2 Waveform 2 Waveform 1 Test Circuit and Waveforms Waveform 3 TEST CONDITION Waveform 1, 2 Waveform 2 Waveform 1 Test Circuit and Waveforms Waveform 3
ns ns ns ns ns UNIT ns ns ns ns ns
NOTES: 1. tPNactual - tPMactual for any data input to output path compared to any other data input to output path where N and M are either LH or HL. Skew times are valid only under same test conditions (temperature, VCC, loading, etc.).
1995 May 25
9
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
AC WAVEFORMS
AIn, Bn or Bn OEBn VM tPLH VM VM tPHL VM AOn, Bn AIn, Bn OEB0 VM tPHL VM VM tPLH VM
AOn or Bn
Waveform 1. Propagation Delay for Data or Output Enable to Output
AIn, Bn VM tSK(o) AOn, Bn VM
Waveform 2. Propagation Delay for Data or Output Enable to Output
OEA
VM tPZH
VM tPHZ VM
Waveform 3. Output Skews
VOH -0.3V OV
OEAn
VM tPZL
VM tPLZ VM VOL +0.3V
AOn
AOn
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
SG00079
NOTE: VM = 1.55V for Bn, VM = 1.5V for all others.
1995 May 25
10
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
TEST CIRCUIT AND WAVEFORMS
VCC BIAS V RL 7.0V NEGATIVE PULSE 90% VM 10% tTHL CL RL tW VM 10% LOW V tTLH VIN
90%
VIN PULSE GENERATOR RT D.U.T.
VOUT
(tf) (tr)
90% VM tW
(tr) (tf)
VIN
tTLH 90% POSITIVE PULSE VM 10%
tTHL
Test Circuit for 3-State Outputs on A Port
10%
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
SWITCH POSITION TEST tPLZ, tPZL All other SWITCH closed open Family FB+
VCC BIAS V 2.0V (for RU = 9 ) 2.1V (for RU = 16.5 )
Input Pulse Definitions
INPUT PULSE REQUIREMENTS Amplitude 3.0V 2.0V Low V 0.0V 1.0V Rep. Rate 1MHz 1MHz tW tTLH tTHL 2.5ns 2.5ns
A Port B Port
500ns 2.5ns 500ns 2.5ns
VIN PULSE GENERATOR RT D.U.T.
VOUT
RU
CD
Test Circuit for Outputs on B Port
DEFINITIONS: RL = Load Resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. CD = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00059
1995 May 25
11
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
SOT379-1
1995 May 25
12
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
NOTES
1995 May 25
13
Philips Semiconductors
Product specification
7-bit Futurebus+ transceiver
FB2041
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 08-98
Philips Semiconductors
1995 May 25 14

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